1. Field of the Invention
The present invention generally relates to a programmable delay circuit and, more particularly, is directed to a programmable delay circuit in which linearity of delay characteristic is improved and power consumption is reduced and which is suitably applied to an IC (integrated circuit) tester or the like.
2. Description of the Prior Art
A Digitally Programmable Delay Chip with picosecond Resolution in IEEE Proceedings of the 1989 Bipolar Circuit and Technology Meetings Sep. 18-19, 1989, pp. 295 to 297 describes a conventional programmable delay circuit.
A block diagram forming FIG. 1 shows an example of such a conventional programmable delay circuit.
As shown in FIG. 1, a main or coarse delay circuit 1 is composed of 32 delay gates G.sub.0 to G.sub.31 connected in cascade, a multiplexer 1a and a latch circuit 1b. The latch circuit 1b latches a digital signal of 5 bits (D.sub.0 to D.sub.4) input thereto from a control circuit (not shown) and the multiplexer 1a is controlled in response to the digital output of the latch circuit 1b, thereby pulse signals applied to input terminals IN and INB being delayed by an arbitrary delay time of 110 picoseconds per gate. A cascade circuit 2 is connected to an output of the multiplexer 1a to expand the delay time and composed of a multiplexer 2a and a latch circuit 2b which latches a digital signal D.sub.5. An output of the cascade circuit 2 is supplied through a buffer stage 3 to output terminals Q1 and Q1B, respectively, and a sub or fine tune circuitry 4 is connected to the output of the cascade circuit 2.
FIG. 2 is a schematic block diagram showing an example of a conventional multiplexer, and as shown in FIG. 2, the multiplexer 1a of FIG. 1 is generally comprised of 8 stages of delay gates G.sub.1 to G.sub.8 and seven multiplexers A through G which are supplied with control signals S.sub.0 to S.sub.6 delivered from the latch circuit 1b.
However, in the conventional delay circuit of FIG. 2, the multiplexer 1a is composed of seven multiplexers A through G connected in a so-called tournament fashion, which needs 2.sup.n -1 multiplexers if there are provided 2.sup.n delay circuits. Further, since the signal is passed through n multiplexers from each of the delay gates to the output terminal Q.sub.1, the fixed delay time is increased. In that case, if n is increased, delay error caused by the multiplexer 1a from each of the delay gates to the output terminal Q.sub.1 is increased, thus deteriorating linearity of delay characteristic more.
Furthermore, since the pulse signals supplied to the input terminals IN and INB are passed through the n multiplexers (e.g., the multiplexers A, E and G), the power consumption is increased.